1. Field of the Invention
The present invention relates to a system clock synchronization circuit, and more particularly, to a system synchronization circuit which, even in the case where noise is superimposed on the clock signal received, is capable of supplying correct input data and a correct input enable signal in synchronization with the system clock, which are to be supplied to circuits downstream of the system clock synchronization circuit comprising a digital broadcast reception device.
2. Description of the Related Art
As illustrated in FIG. 12, a digital broadcast reception device includes: a tuner 121 which receives a broadcast signal and selects a channel; an A/D converter 122A which converts an output signal from the tuner 121 to a digital signal; a demodulation circuit 122B which demodulates a digital signal from the A/D converter 122A; an error correction circuit 122C which corrects error data created in the transmission paths; buffers 123A, 123B and 123C; a system clock synchronization circuit 124; a stream separation circuit 125; and an MPEG decoder 126.
Here, the A/D converter 122A, the demodulation circuit 122B and the error correction circuit 122C constitute a reception signals preprocessing circuit 122, which sends out reception data Sdata′, a reception enable signal Sen′ and reception clock CLK′.
The reception data Sdata′, the reception enable signal Sen′ and the reception clock CLK′ are driven by the buffers 123A, 123B and 123C, which momentarily come to have high impedance on the rising and the falling edges, and enter the system clock synchronization circuit 124 as input data Sdata, an input enable signal Sen and input clock CLK, respectively.
The system clock synchronization circuit 124 takes in the input data Sdata, the input enable signal Sen, the input clock CLK and the system clock SCLK, and sends out output data Vdata which is obtained by synchronizing the input data with the system clock SCLK and an output enable signal Ven which is synchronized with the system clock SCLK.
The stream separation circuit 125 takes in the output data Vdata and the output enable signal Ven and separates multiplex stream data into individual stream data, which is then decoded by the MPEG decoder 126 according to the MPEG format.
Next, the operation of the system clock synchronization circuit 124 illustrated in FIG. 12 will be described more specifically with reference to a timing chart illustrated in FIG. 13.
The reception data Sdata′ and the reception enable signal Sen′ are sent out from the reception signals preprocessing circuit 122 in such a manner that they are synchronized with the reception clock CLK′ and change on the falling edge of the reception clock CLK′. That is, the reception data Sdata′ and the reception enable signal Sen′ represent data in units of one reception clock CLK′.
The reception data Sdata′ includes valid data which is used by the MPEG decoder 126 during decoding and invalid data which is on the other hand discarded. In FIG. 13, the invalid data is designated by hatched lines stroked down to the lower left. When the reception enable signal Sen′ becomes active, that is, is set as “1” in the case of FIG. 13, the valid data is sent out from the reception signals preprocessing circuit 122. When the reception enable signal Sen′ becomes inactive, that is, is set as “0” in the case of FIG. 13, the invalid data is sent out from the reception signals preprocessing circuit 122. Hatched lines stroked down to the lower left appearing in the input data Sdata and the output data Vdata also designate invalid data.
In FIG. 13, when the reception enable signal Sen′ synchronizes to the falling edge of the reception clock CLK′ and becomes “1” at time t2, the reception data Sdata′ changes from invalid data to valid data 1, and this valid data 1 is driven by the buffer 123A and enters the system clock synchronization circuit 124 as the input data Sdata. Similarly, the reception enable signal Sen′ which becomes “1” at time t2 is driven by the buffer 123B and enters the system clock synchronization circuit 124 as the input enable signal Sen with a delay due to the buffer 123B.
Next, at time t3, synchronizing to the rising edge of the input clock CLK, the system clock synchronization circuit 124 takes in the valid data 1. Then at time t4, synchronizing to the system clock SCLK, the system clock synchronization circuit 124 sends out this data to the stream separation circuit 125 as the output data Vdata.
The output enable signal Ven which rises to “1” at time t4 is generated by the system clock synchronization circuit 124 as a pulse signal which keeps “1” for one cycle duration of the system clock SCLK and is sent out to the stream data separation circuit 125 while synchronizing to the system clock SCLK.
Similarly, at time t6, synchronizing to the rising edge of the input clock CLK, the system clock synchronization circuit 124 takes in valid data 2 and, synchronizing to the system clock SCLK at time t7, sends out this data to the stream separation circuit 125 as the output data Vdata.
The output enable signal Ven which rises to “1” at time t7 is generated by the system clock synchronization circuit 124 as a pulse signal which keeps “1” for one cycle duration of the system clock SCLK and sent out to the stream data separation circuit 125 while synchronizing to the system clock SCLK.
As described above, the input data Sdata, the input enable signal Sen and the input clock CLK are synchronized to the system clock SCLK, and are sent out from the system clock synchronization circuit 124 to the stream separation circuit 125 as the output data Vdata and the output enable signal Ven, both of which have been synchronized to the system clock SCLK.
Next, details of the system clock synchronization circuit 124 will be described with reference to FIG. 14.
The system clock synchronization circuit 124 illustrated in FIG. 14 comprises: a flip-flop circuit 141 which takes in the input enable signal Sen and operates in synchronization with the input clock CLK; a flip-flop circuit 142 which takes in the input data Sdata and operates in synchronization with the input clock CLK; an OR gate 143 which takes in the reset signal as one input; a synchronization circuit 144 which sends out a signal S2 which is obtained by synchronizing a signal S1 sent out from the flip-flop circuit 141 with the system clock signal SCLK; a mask signal generation circuit 145 which takes in the signal S2 and generates a mask signal S5 having a pulse width of one cycle duration of the system clock SCLK; a flip-flop circuit 146 which takes in the mask signal S5 and sends out the output enable signal Ven while synchronizing to the system clock SCLK; and a write enable flip-flop circuit 147 which takes in the mask signal S5 at the write enable terminal we, takes in the output signal S6 from the flip-flop circuit 142 and sends out the output data Vdata while synchronizing to the system clock SCLK. The mask signal generation circuit 145 sends out the mask signal S5 to the OR gate 143 and, when the mask signal S5 assumes the value “1”, resets the flip-flop circuit 141 through the OR gate 143.
Here, if the mask signal S5 is “1”, then the write enable flip-flop circuit 147 operates as a typical flip-flop circuit, and if “0”, then it does not latch input data but keeps previous data. Moreover, a reset signal Rset becomes active, resetting the whole system, before the start of the reception by a digital broadcast reception device. The reset signal is cancelled later.
Next, an example of the mask signal generation circuit 145 will be described with reference to FIG. 15. Here, the synchronization circuit 144 of FIG. 14 is constituted of the flip-flop circuit 1441 illustrated in FIG. 15.
The mask signal generation circuit 145 illustrated in FIG. 15 comprises:    a flip-flop circuit 1451 which sends out a signal S3 which is obtained by synchronizing the signal S2 with system clock SCLK from the flip-flop circuit 1441;    a flip-flop circuit 1452 which sends out a signal S4 which is obtained by synchronizing, the signal S3 with system clock SCLK from the flip-flop circuit 1451; an inverter 1453; and an AND gate 1454.
Here, the flip-flop circuit 1452, the inverter 1453 and the AND gate 1454 generate a mask signal S5 which synchronizes to the rising edge of the signal S3 and has a pulse width of one cycle duration of the system clock SCLK.
Next, the normal operation of the system clock synchronization circuit 124 illustrated in FIGS. 14 and 15 will be described with reference to a timing chart shown in FIG. 16.
In FIG. 16, the input data Sdata changes from invalid data to valid data 1 and enters the system clock synchronization circuit 124 at time t10, and changes from valid data 1 to valid data 2 and enters the system clock synchronization circuit 124 at time t13.
However, as shown in FIG. 12, since the input data Sdata and the input enable signal Sen are those which are driven and generated by the buffers 123A and 123B which come to have high impedance on the falling edge of the input clock CLK, they become indeterminate data on the falling edge of the input clock CLK.
In FIG. 16, these indeterminate data are designated by hatched lines stroked down to the lower right. As shown in the figure, the input data Sdata first changes from the valid data 1 to the indeterminate data and then to the valid data 2 before entering the system clock synchronization circuit 124.
Similarly, the input data Sdata first changes from the valid data 2 to the indeterminate data and then to the valid data 3, and enters the system clock synchronization circuit 124 while synchronizing to the input clock CLK. Similarly, the input enable signal Sen becomes indeterminate at times t10 and t13 on the falling edge of the input clock CLK as illustrated by the hatched lines stroked down to the lower right.
Next, at time t11, synchronizing to the rising edge of the input clock CLK, the flip-flop circuit 142 takes in the valid data 1, and sends it out as a signal S6 to the write enable flip-flop circuit 147. Furthermore, the flip-flop circuit 141 takes in data for which the input enable signal is “1” and sends it out as a signal S1 to the flip-flop circuit 1441.
Next, at time t12, the flip-flop circuit 1451 latches the “1” and sends out a signal S3 which rises to “1” at time t13, which is one cycle duration later of the system clock SCLK. The circuit which is constituted of the flip-flop circuit 1452, the inverter 1453 and the AND gate 1454 rises in synchronization with the rising of the signal S3, and sends out the mask signal S5 having a pulse width of one cycle duration of the system clock SCLK to the flip-flop circuit 146, the write enable terminal we of the write enable flip-flop circuit 147 and the OR gate 143. If the mask signal S5 becomes “1”, then the flip-flop circuit 141 is reset through the OR gate 143 and fall to “0”.
Moreover, at time t14, the flip-flop circuit 146 takes in the mask signal S5 of “1” level, and sends out the mask signal S5 of “0” level after one cycle duration of the system clock SCLK. In other words, the flip-flop circuit 146 sends out the output enable signal Ven which is obtained by delaying the mask signal S5 by one cycle duration of the system clock SCLK.
As described above, the input data Sdata, the input enable signal Sen and the input clock CLK, which enter the system clock synchronization circuit, are synchronized to the system clock SCLK and sent out from the system clock synchronization circuit 124 to the stream separation circuit 125 as the output data Vdata and the output enable signal Ven which are in synchronization with the system clock SCLK.
Next, the operation of the system clock synchronization circuit illustrated in FIGS. 14 and 15 in the case where noise is superimposed on the falling edge of the input clock CLK will be described with reference to FIG. 17.
First, the reason why noise is superimposed on the falling edge of the input clock CLK will be described. Since the input data Sdata and the input enable signal Sen are those which synchronize and change on the falling edge of the input clock CLK, the buffers 123A and 123B momentarily discharge a large current on the falling edge of the input clock CLK. This large current creates a pulse noise, which superimposes on the falling edge of the input clock CLK via crosstalk capacities between transmission paths for the input data Sdata and the input clock CLK and transmission paths for the input enable signal Sen and the input clock CLK.
When this takes place, the buffer 123C which drives the input clock CLK has come to have high impedance and is highly sensitive to a noise, being likely to pick up noises, and the input clock CLK becomes 0 and then jumps to 1 on the falling edge, momentarily exhibiting a pulsed wave shape as illustrated by A and B in FIG. 17.
In the system clock synchronization circuit illustrated in FIGS. 14 and 15, the input clock CLK directly enters the flip-flop circuits 141 and 142. Therefore, if a noise whose width is less than one cycle duration of the system clock SCLK is superimposed on the falling edge of the input clock CLK, then the flip-flop circuits 141 and 142 wrongly see it as the rising edge of the input clock CLK and latch the input data Sdata and the input enable signal Sen with wrong timing, resulting in the malfunction of the system clock synchronization circuit.
Next, the malfunction of the system clock synchronization circuit due to the noise will be described more specifically with reference to FIGS. 15 and 17.
At time t21, synchronizing to the input clock CLK, the flip-flop circuit 141 latches the input enable signal Sen which has become indeterminate and sends it out to the flip-flop circuit 1441 as the signal S1, and the flip-flop circuit 142 takes in the input data Sdata which has become indeterminate and sends it out to the write enable flip-flop circuit 147 as the signal S6.
Next, at time t22, synchronizing to the rising edge of the system clock SCLK, the flip-flop circuit 1451 latches the indeterminate data of the signal S1 and, at time t23 which is one cycle duration later of the system clock SCLK, sends it out to the flip-flop circuit 1452 as the output signal S3.
The circuit which is constituted of the flip-flop circuit 1452, the inverter 1453 and the AND gate 1454 latches the signal S3 and sends out to the flip-flop circuit 146 the indeterminate data of the mask signal S5 which has a pulse width of one cycle duration of the system clock SCLK. And, when the mask signal S5 becomes “1”, the flip-flop circuit 141 is reset through the OR gate 143 and falls to “0”.
Next, at time t24, synchronizing to the rising edge of the system clock SCLK, the write enable flip-flop circuit 147 latches indeterminate data of the signal S6 and sends it out as the output data Vdata. Moreover, synchronizing to the rising edge of the system clock SCLK, the flip-flop circuit 146 latches indeterminate data of the signal S5 and sends it out as the output enable signal Ven. At time t25, this output enable signal Ven changes to “0” in the flip-flop circuit 146, which is the result of latching the mask signal S5 of “0” level in synchronization with the rising edge of the system clock SCLK.
As described above, if a noise whose width is smaller than one cycle duration of the system clock SCLK is superimposed on the falling edge of the input clock CLK, then the flip-flop circuits 141 and 142 wrongly see it as the rising point of the input clock CLK, latches indeterminate data and sends them out to a next circuit. As a result, these indeterminate data successively transmits through the circuits, and the output data Vdata and the output enable data Ven which have become indeterminate end up being sent out to the stream separation circuit 125.
As a result, the stream separation circuit 125 and the MPEG decoder 126 which constitute a conventional digital broadcast reception device cannot process a mixture of normal data and indeterminate data, separating one from another, and operate in a wrong manner.
In the above-described conventional system clock synchronization circuit, the noise from onboard buffers is coped with inserting noise filters on board. However, the result of noise simulation to determine what sort of filters be placed where on board is far from representing the actual noise, and the truth is that designing board in a trial-and-error fashion is unavoidable.
For this reason, it would take a long period of time to reduce noise to a satisfactory level. It would also pose a problem with respect to production costs as it becomes necessary to add parts on board designed to reduced noise.
Accordingly, it is an object of the present invention that a system clock synchronization circuit be provided which does not send out wrong output data and a wrong output enable signal but is capable of sending out correct output data and a correct output enable signal in synchronization to the system clock even in the case where noise is superimposed on the input clock CLK.